Not applicable.
Not applicable.
(1) Field of the Invention
The present invention generally relates to semiconductor integrated circuit (IC) devices. More particularly, this invention relates to a method and structure for solder-mounting a leadless IC package to a substrate equipped with thermal vias, and for preventing solder from entering the vias during solder reflow.
(2) Description of the Related Art
Various packaging configurations have been proposed for mounting IC devices to circuit boards and other electronic substrates. Conventional packages typically require wire leads that electrically connect the package to contact pads on the surface of the circuit board. Leadless packages have been developed that do not have wire leads, but instead have input/output (I/O) pads exposed at a surface of the package. Such packages are known in the industry as quad flat non-leaded (QFN) packages. An example is a QFN package commercially available from Amkor Technology under the name Microleadframe (MLF). As represented in FIG. 1, the Amkor MLF package is a plastic-encapsulated IC package 30 with a copper leadframe 46 that defines lands (I/O pads) 40 near the outer perimeter of the package 30. An IC device 42 is attached to a die paddle (thermal pad) 32 located on the same surface of the package 30 as the pads 40 and surrounded by the pads 40. Wire leads 44 electrically connect the IC device 42 to the I/O pads 40, which in turn are electrically and mechanically connected with solder joints to contact pads on a circuit board or other suitable substrate. The thermal pad 32 promotes heat transfer from the IC device 42 to the circuit board. The circuit board can be equipped with a thermal pad on its surface for contact with the thermal pad 32 of the package 30 to promote heat transfer and dissipation in the circuit board. Heat transfer is promoted by soldering the thermal pad 32 to the thermal pad of the circuit board, and further by forming plated vias (plated through-holes, or PTH""s) in the thermal pad of the circuit board to promote heat transfer through the circuit board to the surface opposite the package 30, where a heat sink or other suitable means can be provided for dissipating heat.
The solder joints at the I/O pads of a leadless package must be sufficiently thick (in the direction normal to the pads) to be compliant for surviving numerous thermal cycles. Solder joint height at the pads is affected by the relatively large volume of solder present between the thermal pads of the package and circuit board. If thermal vias are present in the thermal pad of the circuit board, loss of solder through the vias during reflow can cause the package to collapse toward the circuit board, reducing solder joint height. FIGS. 2 through 4 show a solution proposed in the past to prevent solder wicking into thermal vias. FIG. 2 represents the surface of a substrate 112 prepared for mounting a leadless package, e.g., the package 30 of FIG. 1. The substrate 112 is shown as having a thermal pad 114 surrounded by input/output pads 116, and with plated thermal vias 118 in the thermal pad 114 and extending through the substrate 112. A solder mask is shown as having been applied to the surface of the substrate 112, with openings 124 and 126 patterned in the solder mask to define an outer mask portion 120 surrounding the thermal pad 114 and interior mask portions 122 covering each of the vias 118, thereby plugging or xe2x80x9ctentingxe2x80x9d the vias 118. As represented in FIG. 3, solder paste 134 is then applied to the thermal pad 114, and the leadless package 30 is placed on the substrate 112 so that its thermal pad 32 is registered with the solder paste 134. Solder paste is also deposited on the contact pads 116 (shown in FIG. 2) at the same time as the paste 134 is deposited on the thermal pad 114, such that the I/O pads 40 of the package 30 also register with solder paste. The solder paste 134 is then reflowed to form a solder joint 136 between the thermal pads 114 and 32, as depicted in FIG. 4, as well as solder joints that electrically connect the I/O pads 40 to the contact pads 116.
FIGS. 3 and 4 show the vias 118 as also being closed by solder masks 128 applied to the lower surface of the substrate 112. In practice, only one of the sets of solder masks 122 or 128 would typically be used to plug the vias 118. Reported experiments suggest that masking the vias 118 at the surface of the thermal pad 114 (with solder masks 122) provides better results in terms of reducing void formation during reflow.
The present invention is directed to a method and circuit structure for mounting a leadless IC device to a substrate, such as a circuit board. The method and structure are directed to mounting a leadless device to a substrate having a thermal pad on a first surface thereof, a plurality of contact pads surrounding the thermal pad, and one or more plated vias in the thermal pad and extending through the substrate to an oppositely-disposed second surface of the substrate. The leadless device comprises a thermal pad disposed at a surface of the leadless device for alignment with the substrate thermal pad, a plurality of input/output pads surrounding the device thermal pad for alignment with the contact pads of the substrate, and an integrated circuit device electrically connected to the input/output pads. The leadless device is attached to the substrate with solder that thermally connects the device thermal pad to the substrate thermal pad. To prevent solder flow into the plated vias during reflow, solder mask is provided on the first surface of the substrate, at least a portion of which is deposited on the substrate thermal pad and surrounds the plated via but does not block the plated via. In this manner, the portion of the solder mask defines a barrier between the solder and the plated via, but allows for outgassing through the via during the reflow process.
In view of the above, the present invention provides a solution to the problem of solder wicking through thermal vias during reflow, without resorting to blocking the vias as was believed necessary in the past. As a result, solder joints having adequate thicknesses can be readily achieved, promoting the reliability of the leadless device. An added benefit is the reduction in voids within the solder joint between the thermal pads of the leadless device and substrate as a result of the vias enabling flux outgassing during solder reflow. The solder mask remains as a permanent structure between the leadless device and the substrate, and can be selectively applied to closely surround the perimeters of the individual vias so that the remaining surface of the substrate thermal pad is exposed for attachment with solder to the leadless device. The solder mask can also be patterned to define a grid through which limited surface regions of the substrate thermal pad are exposed, creating multiple solder joints defined between the thermal pads of the leadless device and substrate.
Other objects and advantages of this invention will be better appreciated from the following detailed description.